In trench-gate semiconductor devices, as in other semiconductor devices, the reverse bias breakdown voltage (BVdss) is an important device parameter. In a standard trenchMOS structure, a reverse bias across the device is largely supported in the epitaxial (epi) silicon region. Support of a higher reverse bias without breakdown generally requires both a thicker epi layer and a lower doped epi layer.
However, in the onstate, that is, when there is a forward bias across the device, a lower doped epi layer presents a greater resistance to current flow, as does a thicker layer. This resistance makes a significant contribution to, and may dominate, the forward bias drain-source resistance (Rdson). Rdson is equally an important parameter for the device.
Thus there are two parameters, optimisation of which is potentially conflicting: ideally the device should have a minimum Rdson in order to limit the power dissipation within the device when in the on state; however ideally a device should have a high BVdss in order to maximise the reverse bias which the device can withstand.
In general, where BVdss is governed by the breakdown of a linearly doped one-sided junction (that is, for example, a p+n-diode), it is possible to calculate a relationship between Rdson and BVdss. This relationship is known as the fundamental 1D breakdown limit and is given byRdson=5.93×10−4×BVdss2.5mΩmm2 
Thus, for example, a 30V technology with a typical BVdss of 35V will exhibit a 1D specific epi Rdson of 4mΩmm2, ignoring the resistances of the substrate and channel.
To breach this 1D limit, it has become common place to use so called RESURF structures. A RESURF structure is one which results in a REduced SURface Field. RESURF structures have been implemented in various ways, including SOI (Silicon On Insulator), lateral DMOS, trench RESURF, and p-RESURF. However, RESURF structures are difficult to design and implement, and maximising performance is problematic. In particular, tight control is required of process parameters such as oxide thickness and doping tolerances. Furthermore, use of a RESURF structure requires corresponding modifications to the edge termination of the device lest the edge termination is not capable of supporting the whole of the BVdss of the active area, in which case the RESURF effect is lost and the device avalanches prematurely in the edge termination. Thus there is a need to provide a device which can approach or breach the 1D breakdown limit, without requiring the complexities of a RESURF structure.
US patent application publication US2002/0153558 discloses a device structure which does not rely on the RESURF principle. It discloses a very thin p-type region which extends beyond the gate. This region shields the gate from gate-drain capacitance but does not significantly enhance the breakdown voltage of the device.